We need to arrange memories from fastest to slowest in terms of access speed:
Registers (D): Fastest (located inside CPU).
Cache Memory (B): Next fastest (very close to CPU, faster than RAM).
RAM (C): Slower than cache.
Hard Disk Drive (A): Slowest (secondary storage).
So the correct order is:
Per unit cost comparison (lowest → highest):
Final Order (increasing per unit cost):
E < B < C < A < D
| List - I | List - II |
| (A) Flash Memory | (I) Oldest and Slowest |
| (B) PMOS | (II) Used in large scale integration (LSI) |
| (C) NMOS | (III) Least power consumption |
| (D) CMOS | (IV) Non volatile RAM which is powered continuously |
Solution:
| List - I | List - II | Match |
|---|---|---|
| (A) Flash Memory | (IV) Non-volatile RAM which is powered continuously | A → IV |
| (B) PMOS | (I) Oldest and slowest | B → I |
| (C) NMOS | (II) Used in large scale integration (LSI) | C → II |
| (D) CMOS | (III) Least power consumption | D → III |
Final Answer: (A) → (IV), (B) → (I), (C) → (II), (D) → (III)
Arrange the following steps of retrieving data from memory unit.
(A) Memory Address Register send address to memory chip
(B) The address is placed on address bus
(C) The control unit sends signal
(D) Data is retrieved and place into the Memory Data Register
Options:
(a) D, C, A, B
(b) A, B, C, D
(c) A, C, D, B
(d) B, D, A, C
1. Memory Address Register (MAR) sends the address → (A)
2. Address is placed on the address bus → (B)
3. Control unit sends the read signal → (C)
4. Data is fetched and stored in Memory Data Register (MDR) → (D)
Correct Order: A → B → C → D
Correct Answer: (b) A, B, C, D
Online Test Series, Information About Examination,
Syllabus, Notification
and More.
Online Test Series, Information About Examination,
Syllabus, Notification
and More.