UGC NET Computer Science Computer Organization And Architecture (COA) Previous Year Questions (PYQs) – Page 1 of 4
Study Stuff for MCA Examinations
Solution
Standard I/O techniques are:
• Programmed I/O
• Interrupt-driven I/O
• Direct Memory Access (DMA)
Rotational I/O and Channelized I/O are not standard CPU I/O techniques.
Thus:
A, B, D are correct.
(A) Maximum speedup that a pipeline can provide is k theoretically.
(B) It is impossible to achieve maximum speedup k in k-segment pipeline.
(C) All segments in pipeline take same time in computation.
Choose the correct answer from the options given below:
Solution
So, statement A is true.
In practical cases, due to pipeline filling time, emptying time, delays and unequal stages, exact maximum speedup $k$ is not achieved.
So, statement B is true.
All pipeline segments need not take exactly the same computation time.
So, statement C is false.
(A) Multiprocessor system is controlled by one operating system.
(B) In Multiprocessor system, multiple computers are connected by the means of communication lines.
(C) Multiprocessor system is classified as multiple instruction stream and multiple data stream system.
Choose the correct answer from the options given below:
Solution
So, statement A is true.
Multiple computers connected through communication lines describes a distributed system or multicomputer system, not a tightly coupled multiprocessor system.
So, statement B is false.
Multiprocessor systems are generally classified as MIMD systems, that means multiple instruction stream and multiple data stream.
So, statement C is true.
Therefore, A and C only are correct.
Solution
Memory required:
$2048 \times 8$
Each chip:
$128 \times 4$
First match word size:
$8 / 4 = 2$ chips per word.
Now match number of words:
$2048 / 128 = 16$
Total chips:
$16 \times 2 = 32$
Solution
Speed hierarchy of memory/storage:
CPU Registers → fastest
SRAM → cache memory
DRAM → main memory
Hard Disk → secondary storage
Magnetic Tape → slowest storage
Order:
C → B → A → E → D
Solution
In synchronous interleaved memory organization,
For $m\ll n$,
$t=m\cdot \frac{T}{n}$
For $m\gg n$,
$t=T$
Solution
A crossbar switch provides a separate path between processor and memory module.
So, multiple connections can be made at the same time without blocking each other.
Therefore, crossbar switch is a non blocking network.
Solution
Effective address:
$EA = ADR + XR$
This is indexed addressing, where the address field is added to the index register.
| List-I | List-II |
| A. Complement | I. Adder |
| B. Ex-OR | II. Instruction decoding |
| C. Accumulator | III. Negative number representation |
| D. Control Unit | IV. Arithmetic and Logic operations |
Solution
Complement → used in negative number representation → III
Ex-OR → used in arithmetic and logic operations → IV
Accumulator → used with adder → I
Control Unit → instruction decoding → II
Correct Matching:
A → III
B → IV
C → I
D → II
| List-I | List-II |
| A. RAID level-2 | I. block-interleaved |
| B. RAID level-3 | II. error-correcting-codes |
| C. RAID level-4 | III. reed-solomon codes |
| D. RAID level-6 | IV. bit-interleaved |
Choose the correct answer from the options given below:
Solution
RAID-2 → error correcting codes (Hamming) → II
RAID-3 → bit interleaved parity → IV
RAID-4 → block interleaved parity → I
RAID-6 → Reed–Solomon codes → III
Correct Matching:
A → II
B → IV
C → I
D → III
UGC NET Computer Science
Online Test Series, Information About Examination,
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and More.
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UGC NET Computer Science
Online Test Series, Information About Examination,
Syllabus, Notification
and More.
View More
