UGC NET Computer Science Operating System Previous Year Questions (PYQs) – Page 1 of 11

Interrupt Service Routine (ISR) steps:

Save processor registers → C

Check which device raised interrupt → D

Service the device → B

Restore processor registers → E

Re-enable interrupt facility → A

Correct sequence:

C, D, B, E, A

Critical region is related to mutual exclusion.

Wait signal is related to Hoare's monitor.

Working set is based on principle of locality.

Deadlock is related to circular wait.

So,

A – II, B – I, C – III, D – IV

Steps in page replacement:

No frame is free → D

Find a frame to replace → A

Free that frame → E

Update the page table → B

Use the freed frame for the new page → C

Assertion A is true because FIFO page replacement may show Belady’s anomaly.

In Belady’s anomaly, increasing the number of page frames can sometimes increase the number of page faults.

Reason R is true, but it is not the correct explanation of Assertion A.

Initial semaphore value = 7

Each P operation decreases the value by 1.

Each V operation increases the value by 1.

So,

$7 - 20 + x = 5$

$x - 13 = 5$

$x = 18$

S1 is false because LRU does not suffer from Belady’s anomaly.

S2 is true because shortest remaining time first may cause starvation for long processes.

S3 is false because each thread has its own stack.

Final Answer: (b) S1, S3 false and S2 is true

• User-Mode Programs have the lowest priority and are preemptible.
• Kernel System Service Routines run in kernel mode and can be preempted by higher priority tasks like interrupts.
• Bottom Half Interrupt Handlers execute after the top half and have higher priority than kernel threads.
• Top Half Interrupt Handlers handle immediate hardware responses and have the highest priority.

Thread spawn → thread gets its own register context → IV

Block thread → CPU switches to another ready thread → III

Jacketing → convert blocking system call to nonblocking → I

Flush → reclaim pages → II

Matching:

A → IV

B → III

C → I

D → II

Batch Multiprogramming → maximize CPU utilization → III

Time sharing → minimize response time → IV

Monitor → user does not directly control processor → II

Reentrant procedures → efficient use of memory → I

Matching:

A → III

B → IV

C → II

D → I