UGC NET Computer Science Structure Of Instructions In CPU Previous Year Questions (PYQs)

In implied addressing mode, the operand is already implied in the instruction.

So, there is no need to specify any operand address separately.

Therefore, implied addressing mode requires the least number of memory references.

Memory size is $512K$ words.

$512K=512\times 1024=2^9\times 2^{10}=2^{19}$

So, address part requires $19$ bits.

There are $2$ addressing modes, direct and indirect.

So, addressing mode part requires:

$\log_2 2=1$ bit

There are $256$ registers.

So, register code part requires:

$\log_2 256=8$ bits

Total instruction size is $32$ bits.

Opcode bits:

$32-(1+8+19)$

$=32-28$

$=4$

So, bits are:

$1,4,8,19$

Statement $(i)$ is false.

Self-relocating code is mainly supported by relative addressing, not by auto increment addressing.

Statement $(ii)$ is false.

Auto increment addressing does not necessarily require an additional ALU. The increment can be handled by the processor hardware.

Statement $(iii)$ is true.

In auto increment addressing mode, the register is incremented according to the size of the data item accessed.

For example, if byte is accessed, increment may be $1$. If word is accessed, increment may be more.

Therefore, only statement $(iii)$ is true.

Memory size is

$256K=256\times 1024=2^8\times 2^{10}=2^{18}$ words

So, address part requires

$18$ bits

Number of registers is

$64=2^6$

So, register code requires

$6$ bits

Instruction size is

$32$ bits

Indirect bit requires

$1$ bit

So, operation code bits are

$32-1-6-18=7$

Therefore, operation code, register code and address part are

$7,6,18$

Direct addressing:

$EA=400$

So, (a) $\rightarrow$ (iii)

Register indirect addressing:

$EA=R_1=200$

So, (b) $\rightarrow$ (i)

Index addressing:

$EA=Address+R_1$

$EA=400+200=600$

So, (c) $\rightarrow$ (iv)

Relative addressing:

Instruction is stored at location $500$, address field is at $501$, so next instruction location is $502$.

$EA=PC+Address$

$EA=502+400=902$

So, (d) $\rightarrow$ (ii)

Hence, correct matching is:

$(a)-(iii),\ (b)-(i),\ (c)-(iv),\ (d)-(ii)$

Direct Addressing:

In direct addressing, the memory address is directly given in the instruction.

So, STA, FFFFA is direct addressing.

a → III

Indirect Addressing:

In indirect addressing, the memory address is given indirectly through a register pair.

In MOV A, M, M represents the memory location pointed by HL register pair.

b → IV

Register Addressing:

In register addressing, operands are registers.

MOV A, B uses registers A and B.

c → II

Immediate Addressing:

In immediate addressing, data is directly given in the instruction.

MVI A, FFH means FFH is directly loaded into A.

d → I

Correct matching:

a-III, b-IV, c-II, d-I