Consider a logic gate circuit, with 8 input lines $(D_0,D_1,\ldots,D_7)$ and 3 output lines $(A_0,A_1,A_2)$ specified by following operations
$A_2=D_4+D_5+D_6+D_7$
$A_1=D_2+D_3+D_6+D_7$
$A_0=D_1+D_3+D_5+D_0$
Where $+$ indicates logical OR operation. This circuit is
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